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CXP81720B/81724B
CMOS 8-bit Single Chip Microcomputer
Description The CXP81720B/81724B is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time-base timer, highprecision timing pattern generation circuit, PWM output, 32kHz timer/counter, remote control reception circuit, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also CXP81720B/81724B provides sleep/stop functions which enables to lower power consumption. 100 pin QFP (PIastic) 100 pin LQFP (PIastic)
Structure Silicon gate CMOS IC
Features * A wide instruction set (213 instructions) which covers various types of data -- 16-bit arithmetic/multiplication and division/Boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) 122s at 32kHz operation (2.7 to 5.5V) * Incorporated ROM capacity 20K bytes (CXP81720B) 24K bytes (CXP81724B) * Incorporated RAM capacity 800 bytes * Peripheral functions -- A/D converter 8 bits, 12 channels, successive approximation method (Conversion time of 20.0s at 16MHz) -- Serial interface Incorporated 8-bit and 8-stage FIFO, 1 channel (Auto transfer for 1 to 8 bytes) 8-bit clock sync type, 1 channel -- Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer 32kHz timer/counter -- High-precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable RTG: 5 pins, 2 channels -- PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency 62kHz/16MHz) DA gate pulse output: 12 bits, 4 channels -- FRC capture unit Incorporated 26-bit and 8-stage FIFO -- PWM output 14 bits, 1 channel -- Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO * Interruption 20 factors, 15 vectors, multi-interruption possible * Standby mode Sleep/stop * Package 100-pin plastic QFP/LQFP * Piggyback/evaluator CXP81800
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E97737-PS
Block Diagram
TEX TX EXTAL XTAL RST MP VDD Vss AVREF AVss INT1/NMI INT2 INT0
2 8 SPC700 CPU CORE
PORT B
AVDD
CLOCK GENERATOR/ SYSTEM CONTROL 8
PORT A
AN0 to AN11
12
A/D CONVERTER
NMI
PA0 to PA7
PB0 to PB7
CS0 SI0 SO0 SCK0 FIFO ROM 20K/24K BYTES RAM 800 BYTES
PORT C
SERIAL INTERFACE UNIT (CH0)
INTERRUPT CONTROLLER
8
PC0 to PC7
PORT D
SI1 SO1 SCK1 2
SERIAL INTERFACE UNIT (CH1)
8
PD0 to PD7
2 6 4 4
PE0 to PE1 PE2 to PE7 PF0 to PF3
TO
8 BIT TIMER 1
PORT F
32kHz TIMER/COUNTER
PORT G
2
PORT H
12 BIT PWM GENERATOR CH0 2
PWM0 DAA0 DAB0 PWM1 DAA1 DAB1 4 19
CH0 5
CH1
ADJ
PPO0/PPO18
RTO3/RTO7
PORT J
12 BIT PWM GENERATOR CH1
PROGRAMMABLE PATTERN GENERATOR
RAM
REALTIME PULSE GENERATOR
PORT I
-2-
2 FRC CAPTURE UNIT FIFO FIFO
EXI0
PRESCALER/ TIME BASE TIMER
PORT E
EC
8 BIT TIMER/COUNTER 0
PF4 to PF7
EXI1
RMC
REMOCON INPUT
8
PG0 to PG7
PWM
14 BIT PWM GENERATOR
8
PH0 to PH7
7
PI1 to PI7
8
PJ0 to PJ7
CXP81720B/81724B
CXP81720B/81724B
Pin Assignment (Top View) 100-pin QFP package
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PI3/TO/ADJ
PI4/INT1/NMI
VDD
VSS
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PI6/SO1 PI7/SI1 PE0/INT0 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0 PG1 PG2 PG3 PG4 PG5 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AVDD AVREF AVSS PF4/AN8
TX
TEX
PI1/RMC
PI2/PWM
Note)
1. NC (Pin 90) is always connected to VDD. 2. Vss (Pins 41 and 88) are both connected to GND.
-3-
PF7/AN11
PF6/AN10
PF5/AN9
EXTAL
SCK0
XTAL
RST
SO0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
CS0
VSS
MP
SI0
PI5/SCK1
CXP81720B/81724B
Pin Assignment (Top View) 100-pin LQFP package
PB4/PPO12
PB5/PPO13
PB6/PPO14
PB7/PPO15
PA0/PPO0
PA1/PPO1
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PA7/PPO7
PI3/TO/ADJ
PI4/INT1/NMI
PI5/SCK1
PI1/RMC
PI2/PWM
PI6/SO1
VSS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0 PG1 PG2 PG3 PG4 PG5 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3AN7 AVDD AVREF
TX
TEX
NC
VDD
PF5/AN9
PF4/AN8
PI7/SI1
Note)
1. NC (Pin 88) is always connected to VDD. 2. Vss (Pins 39 and 86) are both connected to GND.
-4-
PF7/AN11
PF6/AN10
EXTAL
SCK0
XTAL
AVSS
SO0
RST
PD2
PD1
PD0
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
CS0
VSS
SI0
MP
PE0/INT0
CXP81720B/81724B
Pin Description Symbol PA0/PPO0 to PA7/PPO7 I/O Output/ Real time output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Description
PB0/PPO8 to PB7/PPO15 PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7
Output/ Real time output I/O/ Real time output I/O/ Real time output
Programmable pattern generator (PPG) output. Functions as high-precision real-time pulse output port. (19 pins)
Real-time pulse generator (RTG) output. Functions as high-precision real-time pulse output port. (5 pins)
PD0 to PD7
I/O
(Port D) 8-bit I/O port. I/O can be set in a unit of 4 bits. Can drive 12mA sink current. (8 pins) Input to request external interruption. Active at the falling edge. External event Input to request external interruption. input for timer/counter. Active at the falling edge. PWM outputs. (2 pins)
PE0/INT0
Input/input
PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4 to PF3/AN7 PF4/AN8 to PF7/AN11 SCK0 SO0 SI0 CS0
Input/input/input Output/output Output/output Output/output Output/output Output/output Output/output Input Input/input (Port E) 8-bit port. Lower 2 bits are for input; upper 6 bits are for output. (8 pins)
DA gate pulse outputs. (4 pins)
Analog inputs to A/D converter. (12 pins) (Port F) 8-bit port. Lower 4 bits are for input; upper 4 bits are for output. Lower 4 bits also serve as standby release input pin. (8 pins) Serial clock I/O (CH0). Serial data output (CH0). Serial data input (CH0). Serial chip select input (CH0).
Output/input I/O Ouput Input Input
-5-
CXP81720B/81724B
Symbol PG0 to PG5 PG6/EXI0 PG7/EXI1 Input
I/O (Port G) 8-bit input port. (8 pins)
Description
Input/input Input/input
External input to FRC capture unit. (2 pins)
PH0 to PH7
Output
(Port H) N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) Remote control reception circuit input. 14-bit PWM output. (Port I) 7-bit I/O port. I/O port can be set in a unit of single bits. (7 pins) Timer/counter, 32kHz oscillation adjustment output. Input to request external interruption and non maskable interruption. Active at the falling edge. Serial clock I/O (CH1). Serial data output (CH1). Serial data input (CH1). (Port J) 8-bit I/O port. I/O and standby release input function can be set in a unit of single bits. Connnects a crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. Connects a crystal oscillator for 32kHz timer/counter clock. When used as event counter, input to TEX pin and leave TX pin open. System reset; active at Low level. Test mode pin. Always connect to GND. Positive power supply of A/D converter.
PI1/RMC PI2/PWM PI3/TO/ADJ PI4/INT1/ NMI PI5/SCK1 PI6/SO1 PI7/SI1 PJ0 to PJ7 EXTAL XTAL TEX TX RST MP AVDD AVREF AVss VDD Vss
I/O/input I/O/output I/O/output/output I/O/input/input I/O/I/O I/O/output I/O/input I/O Input Output Input Output Input Input
Input
Reference voltage input of A/D converter. GND of A/D converter. Positive power supply. GND. Connect both Vss pins to GND.
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CXP81720B/81724B
Input/Output Circuit Formats for Pins Pin Port A Port B PA0/PPO0 to PA7/PPO7 PB0/PPO8 to PB7/PPO15
PPO data
Circuit format
When reset
Ports A, B data
Hi-Z
Output becomes active from high impedance by data writing to port register.
Data bus RD (Port A or B)
16 pins Port C
PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7
Data bus
PPO, RTO data Port C data IP Input protection circuit
Hi-Z
Port C direction "0" when reset
RD (Port C)
8 pins Port D
PD0 to PD7
Port D data IP
Large current 12mA
Hi-Z
Port D direction "0" when reset Data bus
8 pins
RD (Port D)
-7-
CXP81720B/81724B
Pin Port E
Circuit format
Schmitt input
When reset
PE0/INT0 PE1/EC/INT2
IP
Interruption circuit/ event counter Data bus
Hi-Z
2 pins Port E
DA gate output, PWM output Hi-Z control
RD (Port E)
MPX
PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1
Port E data
Hi-Z
Port/DA output select "0" when reset Data bus
4 pins Port E
RD (Port E)
DA gate output Hi-Z control MPX
PE6/DAB0 PE7/DAB1
Port E data
H level
Port/DA output select "1" when reset Data bus
2 pins
RD (Port E)
AN0 to AN3 4 pins Port F
Input multiplexer IP A/D converter
Hi-Z
Input multiplexer
PF0/AN4 to PF3/AN7
IP
A/D converter
Hi-Z
Data bus
4 pins
RD (Port F)
-8-
CXP81720B/81724B
Pin Port F
Circuit format
When reset
PF4/AN8 to PF7/AN11
Port F data
Data bus RD (Port F) Port F function selection "0" when reset
IP
A/D converter
Hi-Z
Input multiplexer
4 pins Port G
PG0 to PG5 6 pins
Schmitt input IP RD (Port G) Note) For PG4 and PG5, CMOS Schmitt input or TTL Schmitt input can be selected with the mask option. Data bus
Hi-Z
Port G PG6/EXI0 PG7/EXI1 2 pins Port H PH0 to PH7
Port H data IP FRC capture unit
Hi-Z
Data bus RD (Port G)
Hi-Z
Data bus Large current 12mA Medium drive voltage 12V RD (Port H)
8 pins Port I
Port I function selection "0" when reset PI2: 14-bit PWM
PI2/PWM PI3/TO/ADJ
PI3:
Timer/counter, 32kHz timer Port I data Port I/O direction "0" when reset
MPX
Hi-Z
IP
Data bus
2 pins
RD (Port I)
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CXP81720B/81724B
PIn Port I
Port I data
Circuit format
When reset
PI1/RMC PI4/INT1/NMI PI7/SI1
Data bus
Port I direction "0" when reset IP RD (Port I) PI1: Remote control circuit PI4: Interruption circuit PI7: Serial interface CH1 Schmitt input
Hi-Z
3 pins Port I
Port I function selection Serial interface CH1
PI5/SCK1 PI6/SO1
MPX
Port I data
Hi-Z
Port I direction "0" when reset Data bus RD (Port I) Serial interface CH1 PI6 is not Schmitt input MPX IP
2 pins Port J
Port J data
PJ0 to PJ7
Data bus
Port J direction "0" when reset IP RD (Port J)
Hi-Z
Edge detection
8 pins
Standby release
CS0 SI0 2 pins
Schmitt input IP CS Serial interface CH0 SI
Hi-Z
SO0
Serial interface CH0
SO
Hi-Z
1 pin
SO output enable
- 10 -
CXP81720B/81724B
PIn
Circuit format
When reset
SCK
SCK0
Serial interface CH0 SCK output enable SCK IP
Hi-Z
1 pin
Schmitt input
EXTAL XTAL
EXTAL
IP
* Diagram shows the circuit composition during oscillation. * Feedback resistor is removed during stop mode. XTAL becomes High level.
Oscillation
2 pins
XTAL
TEX TX
32kHz timer counter TEX IP
* Diagram shows the circuit composition during oscillation. * Feedback resistor is removed during oscillation circuit stop by software. At this time TEX pin outputs Low level and TX pin outputs High level.
Oscillation
2 pins
TX
Pull-up resistor
RST
OP Mask option Schmitt input
L level
1 pin
IP
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CXP81720B/81724B
Absolute Maximum Ratings Item Symbol VDD Supply voltage AVDD AVSS Input voltage Output voltage Medium drive output voltage High level output current High level total output current Low level output current VIN VOUT VOUTP IOH IOH IOL IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL Topr Tstg PD Rating -0.3 to +7.0 AVss to +7.01 -0.3 to +0.3 -0.3 to +7.02 -0.3 to +7.02 -0.3 to +15.0 -5 -50 15 20 130 -20 to +75 -55 to +150 600 380 mW Unit V V V V V V mA mA mA mA mA C C QFP package type LQFP package type Total of all output pins Port H pin Remarks
(Vss = 0V)
Ports excluding large current outputs Large current outputs3 Total of all output pins
1 AVDD and VDD should be set to the same voltage. 2 VIN and VOUT should not exceed VDD + 0.3V. 3 The large current drive transistors are the N-CH transistors of the PD and PH ports. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.
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CXP81720B/81724B
Recommended Operating Conditions Item Symbol Min. 4.5 3.5 2.7 2.5 Analog voltage AVDD VIH High level input voltage VIHS VIHTS VIHEX VIL Low level input voltage VILS VILTS VILEX Operating temperature Topr 4.5 0.7VDD 0.8VDD 2.2 VDD - 0.4 0 0 0 -0.3 -20 Max. 5.5 5.5 5.5 5.5 5.5 VDD VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.8 0.4 +75 V V V V V V V V V C Unit Remarks
(Vss=0V)
Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks V Guaranteed operation range for 1/16 frequency dividing clock and sleep mode Guaranteed operation range by TEX clock Guaranteed data hold range during stop mode 1 2 CMOS Schmitt input3 TTL Schmitt input4 EXTAL pin5 TEX pin6 2 CMOS Schmitt input3 TTL Schmitt input4 EXTAL pin5 TEX pin6
Supply voltage
VDD
1 AVDD and VDD should be set to the same voltage. 2 Normal input port (PC, PD, PE0, PE1, PF0 to PF3, PG, PI and PJ pins), MP pin. 3 CS0, SI0, SCK0, RST, INT0, EC/INT2, PG (For PG4 and PG5, when CMOS Schmitt input is selected with mask option), RMC, INT1/NMI, SCK1 and SI1 pins. 4 PG4 and PG5 pins (When TTL Schmitt input is selected with mask option) 5 Specifies only when the external clock is input. 6 Specifies only when the event count clock is input.
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CXP81720B/81724B
Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH Pins PA to PD, PE2 to PE7, PF4 to PF7, PH (VOL only) PI1 to PI7 PJ, SO0, SCK0 PD, PH IIHE IILE Input current IIHT IILT IILR TEX RST1 PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST1 EXTAL Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -20 to +75C, Vss = 0V) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 Typ. Max. Unit V V V V V A A A A A
VOL
I/O leakage current
IIZ
VDD = 5.5V, VI = 0, 5.5V
10
A
Open drain output leakage current (in N-ch Tr OFF state)
ILOH
PH
VDD = 5.5V VOH = 12V 1/2 frequency dividing clock operation
50
A
IDD1
VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation and termination of 16MHz crystal oscillation (C1 = C2 = 47pF) Sleep mode VDD
22
45
mA
IDDS1
35
100
A
Supply current2
IDD2
VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation, termination of 16MHz crystal oscillation (C1 = C2 = 47pF) Stop mode VDD = 5.5V, termination of 16MHz and 32kHz crystal oscillation
1.1
8
mA
IDDS2
9
30
A
IDDS3
10
A
Input capacity
CIN
Other than Clock 1MHz VDD, Vss, AVDD, 0V for no-measured pins and AVss
10
20
pF
1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. 2 When entire output pins are open.
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CXP81720B/81724B
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count input clock pulse width Event count input clock rise and fall times System clock frequency Event count input clock pulse width Event count input clock rise and fall times 1 (CPU clock selection). Symbol fC Pins XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 Fig. 2 VDD = 2.7 to 5.5V (32kHz clock applied condition) Fig. 3 Fig. 3 32.768 10 20 4tsys1 20 Min. 1 28 200 Max. Unit 16 MHz ns ns ns ns kHz s ms
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
tTL, tTH tTR, tTF
tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
VDD - 0.4V EXTAL 0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied condition
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition crystal oscillation
EXTAL
XTAL
EXTAL
XTAL
TEX
TX C2
C1
C2
74HC04
C1
Fig. 3. Event count clock timing
0.8VDD 0.2VDD
TEX EC
tEH tTH
tEF tTF
tEL tTL
tER tTR
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CXP81720B/81724B
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 float delay time CS0 SO0 delay time CS0 SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High and Low level widths SI0 input setup time (for SCK0 ) SI0 input hold time (for SCK0 ) SCK0 SO0 delay time Note 1) Symbol Pin SCK0
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SO0 SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 50 100 200
tsys + 200
100
tsys + 200
100
ns ns
tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper
2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
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CXP81720B/81724B
Fig. 4. Serial transfer CH0 timing
tWHCS
CS0
0.8VDD
0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
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CXP81720B/81724B
Serial transfer (CH1) Item SCK1 cycle time SCK1 High and Low level widths SI1 input setup time (for SCK1 ) SI1 input hold time (for SCK1 ) SCK1 SO1 delay time Symbol Pins SCK1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Conditions Input mode Output mode Input mode SCK1 Output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SI1 SCK1 output mode SCK1 input mode SO1 SCK1 output mode Min. 1000 16000/fc 400 8000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer CH1 timing
tKCY tKL tKH
SCK1
0.8VDD
0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
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CXP81720B/81724B
(3) A/D converter characteristics Item Resolution Linearity error Absolute error Conversion time Sampling time Symbol
(Ta = -20 to +75C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V) Pins Conditions Min. Typ. Max. 8 Ta = 25C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V 1 2 160/fADC1 12/fADC1 AVREF AVDD - 0.5 0 Operating mode AVREF Sleep mode Stop mode 32kHz operating mode 0.6 1.0 10 AVDD Unit Bits LSB LSB s s V V mA A
tCONV tSAMP
VIAN IREF AN0 to AN11
Reference input voltage VREF Analog input voltage
AVREF current
IREFS
Fig. 6. Definitions of A/D converter terms
FFh FEh
Digital conversion value
Linearity error 01h 00h Analog input
1 The value of fADC is as follows by selecting ADC operation clock (MSC: Address 01FFh bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc
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CXP81720B/81724B
(4) Interruption, reset input Item Symbol
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Pin INT0 INT1 INT2 NMI PJ0 to PJ7 RST Condition Min. Max. Unit
External interruption High and Low level widths
tIH tIL tRSL
1
s
Reset input low level width
32/fc
s
Fig. 7. Interruption input timing
INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge)
tIH
tIL
0.8VDD 0.2VDD
Fig. 8. Reset input timing
tRSL
RST 0.2VDD
(5) Others Item EXI input High and Low level widths Note) Symbol Pin EXI0 EXI1
(Ta = -20 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Min. Max. Unit ns
tEIH tEIL
tsys = 2000/fc
tsys + 200
tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") tFRC [ns] = 1000/fc
Fig. 9. Other timings
tEIH tEIL
EXI0 EXI1
0.8VDD 0.2VDD
- 20 -
CXP81720B/81724B
Appendix Fig. 10. Recommended oscillation circuit
(i) (ii)
EXTAL
XTAL Rd
TEX
TX Rd
C1
C2
C1
C2
Manufacturer
Model
fc (MHz) 8.00
C1 (pF) 10
C2 (pF) 10
Rd ()
Circuit example
RIVER ELETEC CO., LTD.
HC-49/U03
10.00 12.00 16.00 8.00 5 16 16 12 12 30
0 5 12 12 12 12 18 470k 0
(i)
HC-49/U (-S) KINSEKI LTD.
10.00 12.00 16.00
(i)
P3
32.768kHz
(ii)
Models with an asterisk () have the built-in ground capacitance (C1, C2).
Mask option table Item Reset pin pull-up resistor Input circuit format1 Content Non-existent CMOS Schmitt Existent TTL Schmitt
1 The input circuit format can be selected each for PG4 pin and PG5 pin.
- 21 -
CXP81720B/81724B
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25C, Typical) 20.0 10.0 5.0 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode 20
IDD vs. fc
(VDD = 5V, Ta = 25C, Typical) 1/2 dividing mode
IDD - Supply current [mA]
Sleep mode 1.0 0.5 32kHz mode (instruction) 32kHz Sleep mode
IDD - Supply current [mA]
15 1/4 dividing mode
10
0.1 (100A) 0.05 (50A)
5 0.01 (10A) 2 3 4 5 6 7 0 10 5 fc - System clock [MHz]
1/16 dividing mode
Sleep mode 16
VDD - Supply voltage [V]
- 22 -
CXP81720B/81724B
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
+ 0.1 0.15 - 0.05
23.9 0.4 + 0.4 20.0 - 0.1
+ 0.4 14.0 - 0.01 17.9 0.4
15.8 0.4
A
0.65 0.12 M
+ 0.35 2.75 - 0.15
0.15
0 to 15 DETAIL A
0.8 0.2
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.4g
100PIN LQFP (PLASTIC)
16.0 0.2 75 76 14.0 0.1 51 50
100 1 0.5 0.08 + 0.08 0.18 - 0.03 25
26 (0.22)
+ 0.2 1.5 - 0.1
+ 0.05 0.127 - 0.02 0.1
0.1 0.1
0 to 10
DETAIL A
0.5 0.2
NOTE: Dimension "" does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY/PHENOL RESIN SOLDER PLATING 42 ALLOY LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT
SONY CODE EIAJ CODE JEDEC CODE
LQFP-100P-L01 QFP100-P-1414-A
- 23 -
0.5 0.2
A
(15.0)

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